Semiconductor integrated circuit and functional block of the same

ABSTRACT

The burden of developing a complex bridge block imposed on the IP reuser is reduced by introducing a system clock into the IP. The IP composed of a functional circuit of this invention and its synchronizing circuit takes in the system clock by integrating the synchronizing circuit taking in the system clock with the IP functional circuit into the IP in reusing the IP complying with the standard in the development of an LSI with a built-in IP and its derivatives. This enables the reuser to incorporate the IP into the LSI via a simple bridge block, taking into account only the system clock for driving the system bus, which reduces the burden of handling the IP and increases the reusability of the IP.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-196868, filed Jun.29, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to the design of IP (IntellectualProperty), and more particularly to a synchronizing circuit whichenables an exchange of signals between an IP functional circuit and asystem bus using two types of clocks: a local clock for driving the IPfunctional circuit built in an LSI and a system clock for driving thesystem bus.

[0003] Furthermore, the present invention integrates the IP functionalcircuit and the synchronizing circuit into an entity and uses theresulting circuit as an IP (functional block) in the design of an LSI.The invention includes a semiconductor integrated circuit containing theIP functional circuit and synchronizing circuit.

[0004] Using FIG. 1, conventional IP designs will be explained. Some ofthe conventional IP designs depend on the system bus and the others donot depend on the system bus. FIG. 1 shows an example of an IP designdepending on the system bus. Numeral 1 indicates the system bus fortransmitting the input and output signals of an IP. The system busoperates in synchronization with a system clock. Numeral 2 indicates anIP to be designed, which operates in synchronization with the systemclock and local clock.

[0005] In the conventional IP design shown in FIG. 1, since the IP 2itself is designed dependently on a specific system bus 1, the IP 2 canbe used as it is, regardless of the difference in frequency between thesystem clock and local clock, in reusing the IP 2 for the design of anLSI with a specific system bus 1.

[0006] Because the IP vendor must prepare a separate IP for each of thevarious system buses, this decreases the efficiency of the IP vendor. Toavoid this, an IP design independent of the system bus as shown in FIG.2 has been used.

[0007] In FIG. 2, IP 3 indicates a circuit which synchronizes with onlythe local clock and which is connected to the system bus 1 via a bridgeblock 4 that absorbs the difference between the system clock and localclock. Specifically, a circuit 5 composed of the IP 3 and the bridgeblock 4 is connected to the system bus 1 synchronizing with the systemclock.

[0008] The bridge block is a circuit block which enables signal exchangebetween the IP bus synchronizing with the local clock and the system bussynchronizing with the system clock and which includes a circuit thatsynchronizes with both of the local clock and system clock.

[0009] As shown by vertical broken lines and single-dash-dot lines inFIG. 3, the rising or falling edges of the local clock generallycontaining a plurality of clocks have to be synchronized with the systemclock in various modes. Because the duration time of the high level orlow level of the local clock has to be set to a different lengthaccording to the function of the IP, the design of a bridge block iscomplex.

[0010] The bridge block is developed by the IP reuser. Therefore, in theconventional IP design using a bridge block, since the bridge blockabsorbs the difference between clocks, this imposes on the IP reuser theheavy burden of developing a complex circuit constituting a bridgeblock, which causes the problem of lengthening the time required fordevelopment.

[0011] As described above, in the conventional IP design, IP designdependent on the system bus requires the IP vendor to prepare an IPcorresponding to each of the various system buses, whereas IP designindependent of the system bus causes the problem of imposing on the IPreuser the heavy burden of developing a complex bridge block forabsorbing the difference between the system clock and local clock.

BRIEF SUMMARY OF THE INVENTION

[0012] The IP (functional block) of this invention takes in the systemclock by integrating a synchronizing circuit taking in the system clockwith an IP functional circuit into the IP in reusing the IP complyingwith the standard in the development of an LSI with a built-in IP andits derivatives. This enables the reuser to incorporate the IP into theLSI using a simple bridge block, taking into account only the systemclock, which reduces the burden of handling the IP on the IP reuser andincreases the reusability of the IP.

[0013] Specifically, each of a functional block of the present inventionand a semiconductor integrated circuit including the functional block,comprises: a system bus synchronizing with a system clock; a functionalcircuit synchronizing with a local clock; and a synchronizing circuitfor determining the operation timing for signal exchange between thesystem bus and the functional circuit, wherein the synchronizing circuittakes in the system clock and the local clock and determines theoperation timing by determining the access time for the functionalcircuit from the system clock.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0014] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0015]FIG. 1 is a diagram to help explain a conventional IP design;

[0016]FIG. 2 is a diagram to help explain a conventional IP designindependent of the system bus;

[0017]FIG. 3 shows the relationship between the system clock and localclock;

[0018]FIG. 4 is a diagram to help give a general explanation of IPdesign according to a first embodiment of the present invention;

[0019]FIG. 5 shows the configuration of the IP according to the firstembodiment;

[0020]FIG. 6 shows the system clock and timing waveform of registeraccess;

[0021]FIG. 7 is a diagram showing a concrete configuration of the IP;and

[0022]FIG. 8 is a diagram to help explain the operation of a frequencyspecifying signal related to a second embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] In embodiments of the present invention, IP means theintellectual property of a functional block with a specific functionbuilt in an LSI. In developing LSIs and their derivatives, all the dataabout the design of functional blocks and others requiring a long timefor development is handed over as intellectual property and reused indeveloping new products.

[0024] Use of an IP functional circuit, an IP composed of itssynchronizing circuit, and an LSI incorporating these circuits enablesinherited known intellectual property concerning the design of IP to beused effectively in reusing IP functional blocks in LSIs and theirderivatives, which contributes to a reduction in development cost.

[0025] Hereinafter, referring to the accompanying drawings, embodimentsof the present invention will be described in detail.

[0026] <First Embodiment>

[0027] FIGS. 4 to 7 are diagrams to help explain an IP (functionalblock) design that integrates an IP functional circuit according to afirst embodiment of the present invention and its synchronizing circuitinto an entity. Using FIG. 4, the outline of the IP design related tothe first embodiment will be described.

[0028] In the IP design of FIG. 4, an IP (functional block) 20 thattakes in a system clock and operates according to a local clock isconnected to a bridge block 30 that synchronizes only with the systemclock. A circuit 40 composed of the IP 20 and bridge block 30 isconnected to a system bus 10.

[0029] In the IP design of the present invention shown in FIG. 4, thesystem clock is synchronized with the local clock in the IP 20.Therefore, unlike the conventional bridge block 4 (see FIG. 2), thebridge block 30 of the present invention requires only the system clockto be taken into account. This facilitates the design of the bridgeblock, shortening the time required for development.

[0030] Next, using FIG. 5, the configuration of the IP 20 of the firstembodiment will be explained. The IP 20 of FIG. 5 is composed of an IPfunctional circuit 21 synchronizing with the local clock and asynchronizing circuit 22 that takes in the system clock and synchronizeswith the local clock.

[0031] At the stage of designing the IP 20, the frequency of the systemclock is unknown. Using a system clock frequency specifying signalA[n:0] (n is a natural number), the synchronizing circuit 22 built inthe IP 20 takes in information on the system clock (for example,specific frequency) and matches the system clock with the local clock inthe IP 20 via the frequency specifying signal A[n:0], which enables IPdesign corresponding to the frequency of various system clocks.

[0032] The system clock frequency specifying signal A[n:0] is suppliedfrom an external pin of the LSI using the IP 20, an internal pull-up ofthe LSI (connection to an internal power supply voltage level), aninternal pull-down of the LSI (connection to the ground level), or thebridge block 30. The supply of the system clock frequency specifyingsignal A[n:0] from the bridge block 30 would make it possible to copewith a system whose system clock is variable.

[0033] Next, using FIGS. 6 and 7, the operation of the synchronizingcircuit 22 (see FIG. 5) included in the IP 20 will be explained. At thetop of FIG. 6, a timing waveform of the system clock is shown. Thesecond to fourth stages in FIG. 6 show timing waveforms of registeraccess, provided that the IP functional circuit 21 (see FIG. 5)synchronizing with, for example, the local clock is composed of aregister. Here, the system clock is a clock signal for synchronizing allthe signals in the LSI to be transmitted to the system bus 10 (see FIG.4) and the local clock is a clock signal for register access.

[0034] For instance, as shown in the second to fourth stages in FIG. 6,the reading/writing of the register is done in synchronization with thelocal clock on the basis of a read/write signal and chip select signalsupplied from the IP-using LSI. At the time of the completion of theread/write operation, an access end signal is returned to the LSI. Aseries of these operations constitutes a read/write cycle of theregister.

[0035] For instance, in the timing waveform shown in FIG. 6, theconventional bridge block 4 had to synchronize the system clock with thelocal clock in a complex manner to produce the timing waveform necessaryfor register access (for example, see FIG. 3). In contrast, the firstembodiment can produce the timing waveform necessary for register accessusing the system clock and the system clock frequency specifying signalA[n:0].

[0036]FIG. 7 shows a concrete configuration of the IP 20 where the IPfunctional circuit 21 having such a function and the synchronizingcircuit 22 are integrated into an entity. The IP 20 is composed of atiming counter 50, a comparing circuit 60, and an IP functional block 70operating by the local clock.

[0037] As shown in FIG. 7, the timing counter 50 is actuated by the chipselect signal, thereby starting the count of the system clock. Thecomparing circuit 60 compares the count of the timing counter 50 withthe frequency specifying signal A[n:0] and transmits an access endsignal at the time when the result of the comparison has reached aspecific judgment reference.

[0038] On the other hand, the input of the chip select signal andaddress data signal causes the IP functional circuit 70 (register) to beaccessed for processing. Then, in the IP functional circuit 70, a datainput/output cycle (a register read/write cycle) is executed insynchronization with the local clock.

[0039] Externally supplying the system clock frequency specifying signalA[n:0] enables the count of the system clock in the counter to bealigned with the end time of the data input/output cycle of the IPfunctional circuit 70 operating according to the local clock, therebytransmitting an access end signal, which completes a series of datainput/output cycles of the IP functional circuit 70.

[0040] Since the local clock is already known at the time of IP design,the timing with which a key signal is taken in according to the clock isalso known. Then, in the circuit of FIG. 7, the system clock frequencyspecifying signal A[n:0] is externally supplied and the access time isdetermined using the count of the system clock as a reference. Forinstance, measuring the timing of returning the access end signal to theLSI makes it possible to adjust the IP 20 so that it can take in theeffective time of the chip signal.

[0041] <Second Embodiment>

[0042] Using FIG. 8, the operation of a frequency specifying signalA[n:0] related to a second embodiment of the present invention will beexplained. In the first embodiment, the IP 20 has taken in the systemclock using the frequency specifying signal A[n:0] (see FIG. 5) andgenerated a timing waveform for the IP functional circuit 21 operatingaccording to the local clock (see FIG. 6).

[0043] The operation of the frequency specifying signal A[n:0], however,is not effective only when an unknown system clock is matched with theknown local clock in designing the IP 20. In a system that operatesusing two types of clocks, the operation of the frequency specifyingsignal A[n:0] is also effective when the timing of the other type ofclock is matched with a change in the frequency of one type of clock.

[0044] For instance, as shown in FIG. 8, even when the frequencyspecifying signal A[n:0] changes in this order: 000, 001, 010, 011, and100, and accordingly the system clock changes in this order: 20 MHz, 40MHz, 60 MHz, 80 MHz, and 100 MHz, the timing of the local clock can becaused to follow the system clock using the corresponding frequencyspecifying signal A[n:0].

[0045] The operation of the LSI incorporating such an IP is especiallyeffective when the operation modes of the LSI include, for example, alow power operation mode in which a low power operation is possible bylowering the frequency of the system clock.

[0046] Furthermore, the frequency specifying signal A[n:0] allows, forexample, A[n:0] to easily include not only the frequency of the systemclock but also information about changes in the form of the systemclock, such as the ratio of the high level to low level of a square waveconstituting the system clock.

[0047] As explained in the first and second embodiments, since unknowndesign data in designing the IP is only the system clock, when an LSI isdeveloped reusing the IP, giving the specification of an LSI includingthe system clock and the IP inherited as intellectual property and thefrequency specifying signal A[n:0] would enable computer-aided design ofLSIs at least at the register transfer level (RTL).

[0048] The present invention is not limited to the above embodiments.The circuit for taking in two types of clock and making one type ofclock variable for synchronization and the circuit for transmitting theaccess end signal from the IP in synchronization with the system clockcan be realized using circuits or methods other than those explained inFIG. 7. Furthermore, this invention may be practiced or embodied instill other ways without departing from the spirit or essentialcharacter thereof.

[0049] As described above, with the IP design of the present invention,the system clock is synchronized with the local clock. In designing abridge block for causing signal exchange between the system bus and IP,the design of the bridge block is easier, taking only the system clockinto account. This increases the reusability of the IP and itsperipheral functional block in developing an LSI incorporating the IPand its derivatives.

[0050] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A functional block comprising: a system bussynchronizing with a system clock; a functional circuit synchronizingwith a local clock; and a synchronizing circuit for determining theoperation timing for signal exchange between said system bus and saidfunctional circuit, wherein said synchronizing circuit takes in saidsystem clock and said local clock and determines said operation timingby determining the access time of said functional circuit from saidsystem clock.
 2. The functional block according to claim 1, wherein saidsynchronizing circuit takes in said system clock and said local clockand determines said operation timing by creating an access end signalfor said functional circuit from said system clock.
 3. The functionalblock according to claim 2, wherein said access end signal is created byusing a counter actuated in synchronization with said system clock and acomparing circuit to compare the output of said counter with a frequencyspecifying signal.
 4. The functional block according to claim 1, whereinsaid synchronizing circuit determines the operation timing for signalexchange between said system bus and said functional circuit, regardlessof the type of said system bus.
 5. The functional block according toclaim 1, wherein the frequency of said system clock is not fixed to aspecific frequency.
 6. The functional block according to claim 1,wherein the frequency of said system clock is given to create designdata at a register transfer level automatically.
 7. A functional blockcomprising: a system bus synchronizing with a system clock; a functionalcircuit synchronizing with a local clock; and a synchronizing circuitfor determining the operation timing for signal exchange between saidsystem bus and said functional circuit, wherein said functional circuitand said synchronizing circuit are integrated into an entity.
 8. Thefunctional block according to claim 7, wherein said synchronizingcircuit determines the operation timing for signal exchange between saidsystem bus and said functional circuit, regardless of the type of saidsystem bus.
 9. The functional block according to claim 7, wherein thefrequency of said system clock is not fixed to a specific frequency. 10.The functional block according to claim 9, wherein the frequency of saidsystem clock is not fixed to a specific frequency as a result of theinput of a frequency specifying signal to said synchronizing circuit.11. A semiconductor integrated circuit including: a system bussynchronizing with a system clock; a functional circuit synchronizingwith a local clock; and a synchronizing circuit for determining theoperation timing for signal exchange between said system bus and saidfunctional circuit, wherein said synchronizing circuit takes in saidsystem clock and said local clock and determines said operation timingby determining the access time for said functional circuit from saidsystem clock.
 12. The semiconductor integrated circuit according toclaim 11, wherein said synchronizing circuit takes in said system clockand said local clock and determines said operation timing by creating anaccess end signal for said functional circuit from said system clock.13. The semiconductor integrated circuit according to claim 12, whereinsaid access end signal is created by using a counter actuated insynchronization with said system clock and a comparing circuit tocompare the output of said counter with a frequency specifying signal.14. The semiconductor integrated circuit according to claim 11, whereinsaid synchronizing circuit determines the operation timing for signalexchange between said system bus and said functional circuit, regardlessof the type of said system bus.
 15. The semiconductor integrated circuitaccording to claim 11, wherein the frequency of said system clock is notfixed to a specific frequency.
 16. The semiconductor integrated circuitaccording to claim 11, wherein the frequency of said system clock isgiven to create design data at a register transfer level automatically.17. A semiconductor integrated circuit including: a system bussynchronizing with a system clock; a functional circuit synchronizingwith a local clock; and a synchronizing circuit for determining theoperation timing for signal exchange between said system bus and saidfunctional circuit, wherein said functional circuit and saidsynchronizing circuit are integrated into a functional block.
 18. Thesemiconductor integrated circuit according to claim 17, wherein saidsynchronizing circuit determines the operation timing for signalexchange between said system bus and said functional circuit, regardlessof the type of said system bus.
 19. The semiconductor integrated circuitaccording to claim 17, wherein the frequency of said system clock is notfixed to a specific frequency.
 20. The semiconductor integrated circuitaccording to claim 19, wherein the frequency of said system clock is notfixed to a specific frequency as a result of the input of a frequencyspecifying signal to said synchronizing circuit.